Rockchip RK3399 specific extensions to the cdn Display Port with rkfb
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Required properties:
- compatible: must be "rockchip,rk3399-cdn-dp-fb"

- reg: physical base address of the controller and length

- clocks: from common clock binding: handle to dp clock.

- clock-names: from common clock binding:
	       Required elements: "core-clk" "pclk" "spdif"

- resets : a list of phandle + reset specifier pairs
- reset-names : string reset name, must be:
		"spdif"
- power-domains : power-domain property defined with a phandle
		  to respective power domain.
- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
- assigned-clock-rates : the DP core clk frequency, shall be: 100000000

- rockchip,grf: this soc should set GRF regs, so need get grf here.

- phys: from general PHY binding: the phandle for the PHY device.

- extcon: extcon specifier for the Power Delivery

- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF

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Example:
	cdn_dp_fb: dp-fb@fec00000 {
		compatible = "rockchip,rk3399-cdn-dp-fb";
		reg = <0x0 0xfec00000 0x0 0x100000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
			 <&cru SCLK_SPDIF_REC_DPTX>;
		clock-names = "core-clk", "pclk", "spdif";
		assigned-clocks = <&cru SCLK_DP_CORE>;
		assigned-clock-rates = <100000000>;
		power-domains = <&power RK3399_PD_HDCP>;
		phys = <&tcphy0 0>, <&tcphy1 0>;
		resets = <&cru SRST_DPTX_SPDIF_REC>;
		reset-names = "spdif";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		#sound-dai-cells = <1>;
	};
